#ifndef C8051F120_H
#define C8051F120_H 
/*---------------------------------------------------------------------------
;	c8051f120.h - The Device Register Definition 
;
;	Copyright (C) 2007 Our AMCT Corp.
; 	All rights reserved.
;	
;	License Type:	BSD
;	
;	Author:			Xu Chenxiang
;	File Version:	v0.1 (2007/07/11)
;	
;	File History:
;	v0.1 	Inital Release
;
; 	TARGET MCUs	: C8051F120, 'F121, 'F122, 'F123, 'F124, 'F125, "F126, 'F127
;
;---------------------------------------------------------------------------*/

/*  BYTE Registers  */

/*  All Pages */
sfr P0       = 0x80;  /* PORT 0                                        */
sfr SP       = 0x81;  /* STACK POINTER                                 */
sfr DPL      = 0x82;  /* DATA POINTER - LOW BYTE                       */
sfr DPH      = 0x83;  /* DATA POINTER - HIGH BYTE                      */
sfr SFRPAGE  = 0x84;  /* SFR PAGE SELECT                               */
sfr SFRNEXT  = 0x85;  /* SFR STACK NEXT PAGE                           */
sfr SFRLAST  = 0x86;  /* SFR STACK LAST PAGE                           */
sfr PCON     = 0x87;  /* POWER CONTROL                                 */
sfr P1       = 0x90;  /* PORT 1                                        */
sfr P2       = 0xA0;  /* PORT 2                                        */
sfr IE       = 0xA8;  /* INTERRUPT ENABLE                              */
sfr P3       = 0xB0;  /* PORT 3                                        */
sfr PSBANK   = 0xB1;  /* FLASH BANK SELECT                             */
sfr IP       = 0xB8;  /* INTERRUPT PRIORITY                            */
sfr PSW      = 0xD0;  /* PROGRAM STATUS WORD                           */
sfr ACC      = 0xE0;  /* ACCUMULATOR                                   */
sfr EIE1     = 0xE6;  /* EXTERNAL INTERRUPT ENABLE 1                   */
sfr EIE2     = 0xE7;  /* EXTERNAL INTERRUPT ENABLE 2                   */
sfr B        = 0xF0;  /* B REGISTER                                    */
sfr EIP1     = 0xF6;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 1        */
sfr EIP2     = 0xF7;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 2        */
sfr WDTCN    = 0xFF;  /* WATCHDOG TIMER CONTROL                        */

/*  Page 0x00 */
sfr TCON     = 0x88;  /* TIMER CONTROL                                 */
sfr TMOD     = 0x89;  /* TIMER MODE                                    */
sfr TL0      = 0x8A;  /* TIMER 0 - LOW BYTE                            */
sfr TL1      = 0x8B;  /* TIMER 1 - LOW BYTE                            */
sfr TH0      = 0x8C;  /* TIMER 0 - HIGH BYTE                           */
sfr TH1      = 0x8D;  /* TIMER 1 - HIGH BYTE                           */
sfr CKCON    = 0x8E;  /* TIMER 0/1 CLOCK CONTROL                       */
sfr PSCTL    = 0x8F;  /* FLASH WRITE/ERASE CONTROL                     */
sfr SSTA0    = 0x91;  /* UART 0 STATUS                                 */
sfr SCON0    = 0x98;  /* UART 0 CONTROL                                */
sfr SCON     = 0x98;  /* UART 0 CONTROL                                */
sfr SBUF0    = 0x99;  /* UART 0 BUFFER                                 */
sfr SBUF     = 0x99;  /* UART 0 BUFFER                                 */
sfr SPI0CFG  = 0x9A;  /* SPI 0 CONFIGURATION                           */
sfr SPI0DAT  = 0x9B;  /* SPI 0 DATA                                    */
sfr SPI0CKR  = 0x9D;  /* SPI 0 CLOCK RATE CONTROL                      */
sfr EMI0TC   = 0xA1;  /* EMIF TIMING CONTROL                           */
sfr EMI0CN   = 0xA2;  /* EMIF CONTROL                                  */
sfr _XPAGE   = 0xA2;  /* XDATA/PDATA PAGE                              */
sfr EMI0CF   = 0xA3;  /* EMIF CONFIGURATION                            */
sfr SADDR0   = 0xA9;  /* UART 0 SLAVE ADDRESS                          */
sfr FLSCL    = 0xB7;  /* FLASH SCALE                                   */
sfr SADEN0   = 0xB9;  /* UART 0 SLAVE ADDRESS MASK                     */
sfr AMX0CF   = 0xBA;  /* ADC 0 MUX CONFIGURATION                       */
sfr AMX0SL   = 0xBB;  /* ADC 0 MUX CHANNEL SELECTION                   */
sfr ADC0CF   = 0xBC;  /* ADC 0 CONFIGURATION                           */
sfr ADC0L    = 0xBE;  /* ADC 0 DATA - LOW BYTE                         */
sfr ADC0H    = 0xBF;  /* ADC 0 DATA - HIGH BYTE                        */
sfr SMB0CN   = 0xC0;  /* SMBUS 0 CONTROL                               */
sfr SMB0STA  = 0xC1;  /* SMBUS 0 STATUS                                */
sfr SMB0DAT  = 0xC2;  /* SMBUS 0 DATA                                  */
sfr SMB0ADR  = 0xC3;  /* SMBUS 0 SLAVE ADDRESS                         */
sfr ADC0GTL  = 0xC4;  /* ADC 0 GREATER-THAN REGISTER - LOW BYTE        */
sfr ADC0GTH  = 0xC5;  /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE       */
sfr ADC0LTL  = 0xC6;  /* ADC 0 LESS-THAN REGISTER - LOW BYTE           */
sfr ADC0LTH  = 0xC7;  /* ADC 0 LESS-THAN REGISTER - HIGH BYTE          */
sfr TMR2CN   = 0xC8;  /* TIMER 2 CONTROL                               */
sfr TMR2CF   = 0xC9;  /* TIMER 2 CONFIGURATION                         */
sfr RCAP2L   = 0xCA;  /* TIMER 2 CAPTURE REGISTER - LOW BYTE           */
sfr RCAP2H   = 0xCB;  /* TIMER 2 CAPTURE REGISTER - HIGH BYTE          */
sfr TMR2L    = 0xCC;  /* TIMER 2 - LOW BYTE                            */
sfr TL2      = 0xCC;  /* TIMER 2 - LOW BYTE                            */
sfr TMR2H    = 0xCD;  /* TIMER 2 - HIGH BYTE                           */
sfr TH2      = 0xCD;  /* TIMER 2 - HIGH BYTE                           */
sfr SMB0CR   = 0xCF;  /* SMBUS 0 CLOCK RATE                            */
sfr REF0CN   = 0xD1;  /* VOLTAGE REFERENCE 0 CONTROL                   */
sfr DAC0L    = 0xD2;  /* DAC 0 REGISTER - LOW BYTE                     */
sfr DAC0H    = 0xD3;  /* DAC 0 REGISTER - HIGH BYTE                    */
sfr DAC0CN   = 0xD4;  /* DAC 0 CONTROL                                 */
sfr PCA0CN   = 0xD8;  /* PCA 0 COUNTER CONTROL                         */
sfr PCA0MD   = 0xD9;  /* PCA 0 COUNTER MODE                            */
sfr PCA0CPM0 = 0xDA;  /* PCA 0 MODULE 0 CONTROL                        */
sfr PCA0CPM1 = 0xDB;  /* PCA 0 MODULE 1 CONTROL                        */
sfr PCA0CPM2 = 0xDC;  /* PCA 0 MODULE 2 CONTROL                        */
sfr PCA0CPM3 = 0xDD;  /* PCA 0 MODULE 3 CONTROL                        */
sfr PCA0CPM4 = 0xDE;  /* PCA 0 MODULE 4 CONTROL                        */
sfr PCA0CPM5 = 0xDF;  /* PCA 0 MODULE 5 CONTROL                        */
sfr PCA0CPL5 = 0xE1;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH5 = 0xE2;  /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE    */
sfr ADC0CN   = 0xE8;  /* ADC 0 CONTROL                                 */
sfr PCA0CPL2 = 0xE9;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH2 = 0xEA;  /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE    */
sfr PCA0CPL3 = 0xEB;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH3 = 0xEC;  /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE    */
sfr PCA0CPL4 = 0xED;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH4 = 0xEE;  /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE    */
sfr RSTSRC   = 0xEF;  /* RESET SOURCE                                  */
sfr SPI0CN   = 0xF8;  /* SPI 0 CONTROL                                 */
sfr PCA0L    = 0xF9;  /* PCA 0 TIMER - LOW BYTE                        */
sfr PCA0H    = 0xFA;  /* PCA 0 TIMER - HIGH BYTE                       */
sfr PCA0CPL0 = 0xFB;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH0 = 0xFC;  /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE    */
sfr PCA0CPL1 = 0xFD;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE     */
sfr PCA0CPH1 = 0xFE;  /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE    */

/*  Page 0x01 */
sfr CPT0CN   = 0x88;  /* COMPARATOR 0 CONTROL                          */
sfr CPT0MD   = 0x89;  /* COMPARATOR 0 CONFIGURATION                    */
sfr SCON1    = 0x98;  /* UART 1 CONTROL                                */
sfr SBUF1    = 0x99;  /* UART 1 BUFFER                                 */
sfr TMR3CN   = 0xC8;  /* TIMER 3 CONTROL                               */
sfr TMR3CF   = 0xC9;  /* TIMER 3 CONFIGURATION                         */
sfr RCAP3L   = 0xCA;  /* TIMER 3 CAPTURE REGISTER - LOW BYTE           */
sfr RCAP3H   = 0xCB;  /* TIMER 3 CAPTURE REGISTER - HIGH BYTE          */
sfr TMR3L    = 0xCC;  /* TIMER 3 - LOW BYTE                            */
sfr TMR3H    = 0xCD;  /* TIMER 3 - HIGH BYTE                           */
sfr DAC1L    = 0xD2;  /* DAC 1 REGISTER - LOW BYTE                     */
sfr DAC1H    = 0xD3;  /* DAC 1 REGISTER - HIGH BYTE                    */
sfr DAC1CN   = 0xD4;  /* DAC 1 CONTROL                                 */

/*  Page 0x02 */
sfr CPT1CN   = 0x88;  /* COMPARATOR 1 CONTROL                          */
sfr CPT1MD   = 0x89;  /* COMPARATOR 1 CONFIGURATION                    */
sfr AMX2CF   = 0xBA;  /* ADC 2 MUX CONFIGURATION                       */
sfr AMX2SL   = 0xBB;  /* ADC 2 MUX CHANNEL SELECTION                   */
sfr ADC2CF   = 0xBC;  /* ADC 2 CONFIGURATION                           */
sfr ADC2     = 0xBE;  /* ADC 2 DATA                                    */
sfr ADC2GT   = 0xC4;  /* ADC 2 GREATER-THAN REGISTER                   */
sfr ADC2LT   = 0xC6;  /* ADC 2 LESS-THAN REGISTER                      */
sfr TMR4CN   = 0xC8;  /* TIMER 4 CONTROL                               */
sfr TMR4CF   = 0xC9;  /* TIMER 4 CONFIGURATION                         */
sfr RCAP4L   = 0xCA;  /* TIMER 4 CAPTURE REGISTER - LOW BYTE           */
sfr RCAP4H   = 0xCB;  /* TIMER 4 CAPTURE REGISTER - HIGH BYTE          */
sfr TMR4L    = 0xCC;  /* TIMER 4 - LOW BYTE                            */
sfr TMR4H    = 0xCD;  /* TIMER 4 - HIGH BYTE                           */

/*  Page 0x02 */
sfr MAC0BL   = 0x91;  /* MAC0 B Register Low Byte                      */
sfr MAC0BH   = 0x92;  /* MAC0 B Register High Byte                     */
sfr MAC0ACC0 = 0x93;  /* MAC0 Accumulator Byte 0 (LSB)                 */
sfr MAC0ACC1 = 0x94;  /* MAC0 Accumulator Byte 1                       */
sfr MAC0ACC2 = 0x95;  /* MAC0 Accumulator Byte 2                       */
sfr MAC0ACC3 = 0x96;  /* MAC0 Accumulator Byte 3 (MSB)                 */
sfr MAC0OVR  = 0x97;  /* MAC0 Accumulator Overflow                     */
sfr MAC0STA  = 0xC0;  /* MAC0 Status Register                          */
sfr MAC0AL   = 0xC1;  /* MAC0 A Register Low Byte                      */
sfr MAC0AH   = 0xC2;  /* MAC0 A Register High Byte                     */
sfr MAC0CF   = 0xC3;  /* MAC0 Configuration                            */
sfr MAC0RNDL = 0xCE;  /* MAC0 Rounding Register Low Byte               */
sfr MAC0RNDH = 0xCF;  /* MAC0 Rounding Register High Byte              */

/*  Page 0x0F */
sfr FLSTAT   = 0x88;  /* FLASH STATUS                                  */
sfr PLL0CN   = 0x89;  /* PLL 0 CONTROL                                 */
sfr OSCICN   = 0x8A;  /* INTERNAL OSCILLATOR CONTROL                   */
sfr OSCICL   = 0x8B;  /* INTERNAL OSCILLATOR CALIBRATION               */
sfr OSCXCN   = 0x8C;  /* EXTERNAL OSCILLATOR CONTROL                   */
sfr PLL0DIV  = 0x8D;  /* PLL 0 DIVIDER                                 */
sfr PLL0MUL  = 0x8E;  /* PLL 0 MULTIPLIER                              */
sfr PLL0FLT  = 0x8F;  /* PLL 0 FILTER                                  */
sfr SFRPGCN  = 0x96;  /* SFR PAGE CONTROL                              */
sfr CLKSEL   = 0x97;  /* SYSTEM CLOCK SELECT                           */
sfr CCH0MA   = 0x9A;  /* CACHE MISS ACCUMULATOR                        */
sfr P4MDOUT  = 0x9C;  /* PORT 4 OUTPUT MODE                            */
sfr P5MDOUT  = 0x9D;  /* PORT 5 OUTPUT MODE                            */
sfr P6MDOUT  = 0x9E;  /* PORT 6 OUTPUT MODE                            */
sfr P7MDOUT  = 0x9F;  /* PORT 7 OUTPUT MODE                            */
sfr CCH0CN   = 0xA1;  /* CACHE CONTROL                                 */
sfr CCH0TN   = 0xA2;  /* CACHE TUNING REGISTER                         */
sfr CCH0LC   = 0xA3;  /* CACHE LOCK                                    */
sfr P0MDOUT  = 0xA4;  /* PORT 0 OUTPUT MODE                            */
sfr P1MDOUT  = 0xA5;  /* PORT 1 OUTPUT MODE                            */
sfr P2MDOUT  = 0xA6;  /* PORT 2 OUTPUT MODE CONFIGURATION              */
sfr P3MDOUT  = 0xA7;  /* PORT 3 OUTPUT MODE CONFIGURATION              */
sfr P1MDIN   = 0xAD;  /* PORT 1 INPUT MODE                             */
sfr FLACL    = 0xB7;  /* FLASH ACCESS LIMIT                            */
sfr P4       = 0xC8;  /* PORT 4                                        */
sfr P5       = 0xD8;  /* PORT 5                                        */
sfr XBR0     = 0xE1;  /* CROSSBAR CONFIGURATION REGISTER 0             */
sfr XBR1     = 0xE2;  /* CROSSBAR CONFIGURATION REGISTER 1             */
sfr XBR2     = 0xE3;  /* CROSSBAR CONFIGURATION REGISTER 2             */
sfr ADC2CN   = 0xE8;  /* ADC 2 CONTROL                                 */
sfr P6       = 0xE8;  /* PORT 6                                        */
sfr P7       = 0xF8;  /* PORT 7                                        */


/*  BIT Registers  */

/*  P0  0x80 */
sbit P0_0    = 0x80;
sbit P0_1    = 0x81;
sbit P0_2    = 0x82;
sbit P0_3    = 0x83;
sbit P0_4    = 0x84;
sbit P0_5    = 0x85;
sbit P0_6    = 0x86;
sbit P0_7    = 0x87;

/*  TCON  0x88 */
sbit IT0     = 0x88;  /* EXT. INTERRUPT 0 TYPE                         */
sbit IE0     = 0x89;  /* EXT. INTERRUPT 0 EDGE FLAG                    */
sbit IT1     = 0x8A;  /* EXT. INTERRUPT 1 TYPE                         */
sbit IE1     = 0x8B;  /* EXT. INTERRUPT 1 EDGE FLAG                    */
sbit TR0     = 0x8C;  /* TIMER 0 ON/OFF CONTROL                        */
sbit TF0     = 0x8D;  /* TIMER 0 OVERFLOW FLAG                         */
sbit TR1     = 0x8E;  /* TIMER 1 ON/OFF CONTROL                        */
sbit TF1     = 0x8F;  /* TIMER 1 OVERFLOW FLAG                         */

/*  CPT0CN  0x88 */
sbit CP0HYN0 = 0x88;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 0            */
sbit CP0HYN1 = 0x89;  /* COMPARATOR 0 NEGATIVE HYSTERESIS 1            */
sbit CP0HYP0 = 0x8A;  /* COMPARATOR 0 POSITIVE HYSTERESIS 0            */
sbit CP0HYP1 = 0x8B;  /* COMPARATOR 0 POSITIVE HYSTERESIS 1            */
sbit CP0FIF  = 0x8C;  /* COMPARATOR 0 FALLING EDGE INTERRUPT           */
sbit CP0RIF  = 0x8D;  /* COMPARATOR 0 RISING EDGE INTERRUPT            */
sbit CP0OUT  = 0x8E;  /* COMPARATOR 0 OUTPUT                           */
sbit CP0EN   = 0x8F;  /* COMPARATOR 0 ENABLE                           */

/*  CPT1CN  0x88 */
sbit CP1HYN0 = 0x88;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 0            */
sbit CP1HYN1 = 0x89;  /* COMPARATOR 1 NEGATIVE HYSTERESIS 1            */
sbit CP1HYP0 = 0x8A;  /* COMPARATOR 1 POSITIVE HYSTERESIS 0            */
sbit CP1HYP1 = 0x8B;  /* COMPARATOR 1 POSITIVE HYSTERESIS 1            */
sbit CP1FIF  = 0x8C;  /* COMPARATOR 1 FALLING EDGE INTERRUPT           */
sbit CP1RIF  = 0x8D;  /* COMPARATOR 1 RISING EDGE INTERRUPT            */
sbit CP1OUT  = 0x8E;  /* COMPARATOR 1 OUTPUT                           */
sbit CP1EN   = 0x8F;  /* COMPARATOR 1 ENABLE                           */

/*  FLSTAT  0x88 */
sbit FLHBUSY = 0x88;  /* FLASH BUSY                                    */

/*  SCON0  0x98 */
sbit RI0     = 0x98;  /* UART 0 RX INTERRUPT FLAG                      */
sbit RI      = 0x98;  /* UART 0 RX INTERRUPT FLAG                      */
sbit TI0     = 0x99;  /* UART 0 TX INTERRUPT FLAG                      */
sbit TI      = 0x99;  /* UART 0 TX INTERRUPT FLAG                      */
sbit RB80    = 0x9A;  /* UART 0 RX BIT 8                               */
sbit TB80    = 0x9B;  /* UART 0 TX BIT 8                               */
sbit REN0    = 0x9C;  /* UART 0 RX ENABLE                              */
sbit REN     = 0x9C;  /* UART 0 RX ENABLE                              */
sbit SM20    = 0x9D;  /* UART 0 MULTIPROCESSOR EN                      */
sbit SM10    = 0x9E;  /* UART 0 MODE 1                                 */
sbit SM00    = 0x9F;  /* UART 0 MODE 0                                 */

/*  SCON1  0x98 */
sbit RI1     = 0x98;  /* UART 1 RX INTERRUPT FLAG                      */
sbit TI1     = 0x99;  /* UART 1 TX INTERRUPT FLAG                      */
sbit RB81    = 0x9A;  /* UART 1 RX BIT 8                               */
sbit TB81    = 0x9B;  /* UART 1 TX BIT 8                               */
sbit REN1    = 0x9C;  /* UART 1 RX ENABLE                              */
sbit MCE1    = 0x9D;  /* UART 1 MCE                                    */
sbit S1MODE  = 0x9F;  /* UART 1 MODE                                   */

/*  IE  0xA8 */
sbit EX0     = 0xA8;  /* EXTERNAL INTERRUPT 0 ENABLE                   */
sbit ET0     = 0xA9;  /* TIMER 0 INTERRUPT ENABLE                      */
sbit EX1     = 0xAA;  /* EXTERNAL INTERRUPT 1 ENABLE                   */
sbit ET1     = 0xAB;  /* TIMER 1 INTERRUPT ENABLE                      */
sbit ES0     = 0xAC;  /* UART0 INTERRUPT ENABLE                        */
sbit ES      = 0xAC;  /* UART0 INTERRUPT ENABLE                        */
sbit ET2     = 0xAD;  /* TIMER 2 INTERRUPT ENABLE                      */
sbit EA      = 0xAF;  /* GLOBAL INTERRUPT ENABLE                       */

/*  IP  0xB8 */
sbit PX0     = 0xB8;  /* EXTERNAL INTERRUPT 0 PRIORITY                 */
sbit PT0     = 0xB9;  /* TIMER 0 PRIORITY                              */
sbit PX1     = 0xBA;  /* EXTERNAL INTERRUPT 1 PRIORITY                 */
sbit PT1     = 0xBB;  /* TIMER 1 PRIORITY                              */
sbit PS      = 0xBC;  /* SERIAL PORT PRIORITY                          */
sbit PT2     = 0xBD;  /* TIMER 2 PRIORITY                              */

/* SMB0CN 0xC0 */
sbit SMBTOE  = 0xC0;  /* SMBUS 0 TIMEOUT ENABLE                        */
sbit SMBFTE  = 0xC1;  /* SMBUS 0 FREE TIMER ENABLE                     */
sbit AA      = 0xC2;  /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG               */
sbit SI      = 0xC3;  /* SMBUS 0 INTERRUPT PENDING FLAG                */
sbit STO     = 0xC4;  /* SMBUS 0 STOP FLAG                             */
sbit STA     = 0xC5;  /* SMBUS 0 START FLAG                            */
sbit ENSMB   = 0xC6;  /* SMBUS 0 ENABLE                                */
sbit BUSY    = 0xC7;  /* SMBUS 0 BUSY                                  */

/*  TMR2CN  0xC8 */
sbit CPRL2   = 0xC8;  /* TIMER 2 CAPTURE SELECT                        */
sbit CT2     = 0xC9;  /* TIMER 2 COUNTER SELECT                        */
sbit TR2     = 0xCA;  /* TIMER 2 ON/OFF CONTROL                        */
sbit EXEN2   = 0xCB;  /* TIMER 2 EXTERNAL ENABLE FLAG                  */
sbit EXF2    = 0xCE;  /* TIMER 2 EXTERNAL FLAG                         */
sbit TF2     = 0xCF;  /* TIMER 2 OVERFLOW FLAG                         */

/*  TMR3CN  0xC8 */
sbit CPRL3   = 0xC8;  /* TIMER 3 CAPTURE SELECT                        */
sbit CT3     = 0xC9;  /* TIMER 3 COUNTER SELECT                        */
sbit TR3     = 0xCA;  /* TIMER 3 ON/OFF CONTROL                        */
sbit EXEN3   = 0xCB;  /* TIMER 3 EXTERNAL ENABLE FLAG                  */
sbit EXF3    = 0xCE;  /* TIMER 3 EXTERNAL FLAG                         */
sbit TF3     = 0xCF;  /* TIMER 3 OVERFLOW FLAG                         */

/*  TMR4CN  0xC8 */
sbit CPRL4   = 0xC8;  /* TIMER 4 CAPTURE SELECT                        */
sbit CT4     = 0xC9;  /* TIMER 4 COUNTER SELECT                        */
sbit TR4     = 0xCA;  /* TIMER 4 ON/OFF CONTROL                        */
sbit EXEN4   = 0xCB;  /* TIMER 4 EXTERNAL ENABLE FLAG                  */
sbit EXF4    = 0xCE;  /* TIMER 4 EXTERNAL FLAG                         */
sbit TF4     = 0xCF;  /* TIMER 4 OVERFLOW FLAG                         */

/*  P4  0xC8 */
sbit P4_0    = 0xC8;
sbit P4_1    = 0xC9;
sbit P4_2    = 0xCA;
sbit P4_3    = 0xCB;
sbit P4_4    = 0xCC;
sbit P4_5    = 0xCD;
sbit P4_6    = 0xCE;
sbit P4_7    = 0xCF;

/*  PSW  0xD0 */
sbit P       = 0xD0;  /* ACCUMULATOR PARITY FLAG                       */
sbit F1      = 0xD1;  /* USER FLAG 1                                   */
sbit OV      = 0xD2;  /* OVERFLOW FLAG                                 */
sbit RS0     = 0xD3;  /* REGISTER BANK SELECT 0                        */
sbit RS1     = 0xD4;  /* REGISTER BANK SELECT 1                        */
sbit F0      = 0xD5;  /* USER FLAG 0                                   */
sbit AC      = 0xD6;  /* AUXILIARY CARRY FLAG                          */
sbit CY      = 0xD7;  /* CARRY FLAG                                    */

/* PCA0CN D8H */
sbit CCF0    = 0xD8;  /* PCA 0 MODULE 0 INTERRUPT FLAG                 */
sbit CCF1    = 0xD9;  /* PCA 0 MODULE 1 INTERRUPT FLAG                 */
sbit CCF2    = 0xDA;  /* PCA 0 MODULE 2 INTERRUPT FLAG                 */
sbit CCF3    = 0xDB;  /* PCA 0 MODULE 3 INTERRUPT FLAG                 */
sbit CCF4    = 0xDC;  /* PCA 0 MODULE 4 INTERRUPT FLAG                 */
sbit CCF5    = 0xDD;  /* PCA 0 MODULE 5 INTERRUPT FLAG                 */
sbit CR      = 0xDE;  /* PCA 0 COUNTER RUN CONTROL BIT                 */
sbit CF      = 0xDF;  /* PCA 0 COUNTER OVERFLOW FLAG                   */

/*  P5  0xD8 */
sbit P5_0    = 0xD8;
sbit P5_1    = 0xD9;
sbit P5_2    = 0xDA;
sbit P5_3    = 0xDB;
sbit P5_4    = 0xDC;
sbit P5_5    = 0xDD;
sbit P5_6    = 0xDE;
sbit P5_7    = 0xDF;

/* ADC0CN E8H */
sbit AD0LJST = 0xE8;  /* ADC 0 RIGHT JUSTIFY DATA BIT                  */
sbit AD0WINT = 0xE9;  /* ADC 0 WINDOW INTERRUPT FLAG                   */
sbit AD0CM0  = 0xEA;  /* ADC 0 CONVERT START MODE BIT 0                */
sbit AD0CM1  = 0xEB;  /* ADC 0 CONVERT START MODE BIT 1                */
sbit AD0BUSY = 0xEC;  /* ADC 0 BUSY FLAG                               */
sbit AD0INT  = 0xED;  /* ADC 0 EOC INTERRUPT FLAG                      */
sbit AD0TM   = 0xEE;  /* ADC 0 TRACK MODE                              */
sbit AD0EN   = 0xEF;  /* ADC 0 ENABLE                                  */

/* ADC2CN E8H */
sbit AD2WINT = 0xE8;  /* ADC 2 WINDOW INTERRUPT FLAG                   */
sbit AD2CM0  = 0xE9;  /* ADC 2 CONVERT START MODE BIT 0                */
sbit AD2CM1  = 0xEA;  /* ADC 2 CONVERT START MODE BIT 1                */
sbit AD2CM2  = 0xEB;  /* ADC 2 CONVERT START MODE BIT 2                */
sbit AD2BUSY = 0xEC;  /* ADC 2 BUSY FLAG                               */
sbit AD2INT  = 0xED;  /* ADC 2 EOC INTERRUPT FLAG                      */
sbit AD2TM   = 0xEE;  /* ADC 2 TRACK MODE                              */
sbit AD2EN   = 0xEF;  /* ADC 2 ENABLE                                  */

/*  P6  0xE8 */
sbit P6_0    = 0xE8;
sbit P6_1    = 0xE9;
sbit P6_2    = 0xEA;
sbit P6_3    = 0xEB;
sbit P6_4    = 0xEC;
sbit P6_5    = 0xED;
sbit P6_6    = 0xEE;
sbit P6_7    = 0xEF;

/* SPI0CN F8H */
sbit SPIEN   = 0xF8;  /* SPI 0 SPI ENABLE                              */
sbit TXBMT   = 0xF9;  /* SPI 0 TX BUFFER EMPTY FLAG                    */
sbit NSSMD0  = 0xFA;  /* SPI 0 SLAVE SELECT MODE 0                     */
sbit NSSMD1  = 0xFB;  /* SPI 0 SLAVE SELECT MODE 1                     */
sbit RXOVRN  = 0xFC;  /* SPI 0 RX OVERRUN FLAG                         */
sbit MODF    = 0xFD;  /* SPI 0 MODE FAULT FLAG                         */
sbit WCOL    = 0xFE;  /* SPI 0 WRITE COLLISION FLAG                    */
sbit SPIF    = 0xFF;  /* SPI 0 INTERRUPT FLAG                          */

/*  P7  0xF8 */
sbit P7_0    = 0xF8;
sbit P7_1    = 0xF9;
sbit P7_2    = 0xFA;
sbit P7_3    = 0xFB;
sbit P7_4    = 0xFC;
sbit P7_5    = 0xFD;
sbit P7_6    = 0xFE;
sbit P7_7    = 0xFF;


/* Predefined SFR Bit Masks */

#define IDLE              0x01    /* PCON                                */
#define STOP              0x02    /* PCON                                */
#define ECCF              0x01    /* PCA0CPMn                            */
#define PWM               0x02    /* PCA0CPMn                            */
#define TOG               0x04    /* PCA0CPMn                            */
#define MAT               0x08    /* PCA0CPMn                            */
#define CAPN              0x10    /* PCA0CPMn                            */
#define CAPP              0x20    /* PCA0CPMn                            */
#define ECOM              0x40    /* PCA0CPMn                            */
#define PWM16             0x80    /* PCA0CPMn                            */
#define PORSF             0x02    /* RSTSRC                              */
#define SWRSF             0x10    /* RSTSRC                              */


/* SFR PAGE DEFINITIONS */

#define CONFIG_PAGE       0x0F     /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE       0x00     /* LEGACY SFR PAGE                    */
#define TIMER01_PAGE      0x00     /* TIMER 0 AND TIMER 1                */
#define CPT0_PAGE         0x01     /* COMPARATOR 0                       */
#define CPT1_PAGE         0x02     /* COMPARATOR 1                       */
#define UART0_PAGE        0x00     /* UART 0                             */
#define UART1_PAGE        0x01     /* UART 1                             */
#define SPI0_PAGE         0x00     /* SPI 0                              */
#define EMI0_PAGE         0x00     /* EXTERNAL MEMORY INTERFACE          */
#define ADC0_PAGE         0x00     /* ADC 0                              */
#define ADC2_PAGE         0x02     /* ADC 2                              */
#define SMB0_PAGE         0x00     /* SMBUS 0                            */
#define TMR2_PAGE         0x00     /* TIMER 2                            */
#define TMR3_PAGE         0x01     /* TIMER 3                            */
#define TMR4_PAGE         0x02     /* TIMER 4                            */
#define DAC0_PAGE         0x00     /* DAC 0                              */
#define DAC1_PAGE         0x01     /* DAC 1                              */
#define PCA0_PAGE         0x00     /* PCA 0                              */
#define PLL0_PAGE         0x0F     /* PLL 0                              */

#endif

